The well-known Internet network is a notoriously well-known publicly-accessible communication network at the time of filing the present patent application, and arguably the most robust information and communication source ever made available. The Internet is used as a prime example in the present application of a data-packet-network which will benefit from the apparatus and methods taught in the present patent application, but is just one such network, following a particular standardized protocol. As is also very well known, the Internet (and related networks) are always a work in progress. That is, many researchers and developers are competing at all times to provide new and better apparatus and methods, including software, for enhancing the operation of such networks.
In general the most sought-after improvements in data packet networks are those that provide higher speed in routing (more packets per unit time) and better reliability and fidelity in messaging. What is generally needed are router apparatus and methods increasing the rates at which packets may be processed in a router.
As is well-known in the art, packet routers are computerized machines wherein data packets are received at any one or more of typically multiple ports, processed in some fashion, and sent out at the same or other ports of the router to continue on to downstream destinations. As an example of such computerized operations, keeping in mind that the Internet is a vast interconnected network of individual routers, individual routers have to keep track of which external routers to which they are connected by communication ports, and of which of alternate routes through the network are the best routes for incoming packets. Individual routers must also accomplish flow accounting, with a flow generally meaning a stream of packets with a common source and end destination. A general desire is that individual flows follow a common path. The skilled artisan will be aware of many such requirements for computerized processing.
Typically a router in the Internet network will have one or more Central Processing Units (CPUs) as dedicated microprocessors for accomplishing the many computing tasks required. In the current art at the time of the present application, these are single-streaming processors; that is, each processor is capable of processing a single stream of instructions. In some cases developers are applying multiprocessor technology to such routing operations. The present inventors have been involved for some time in development of dynamic multistreaming (DMS) processors, which processors are capable of simultaneously processing multiple instruction streams. One preferred application for such processors is in the processing of packets in packet networks like the Internet.
A dynamic multi-streaming (DMS) processor known to the inventor is capable of utilizing special hardware and a unique queuing system in order to alleviate the packet processing software of the system from certain packet management responsibilities, such as uploading into and downloading packets from memory. The special hardware is described with reference to Ser. No. 09/737,375 listed in the cross-reference section of this specification above. Using acronyms from the cross-referenced specification, the PMU is responsible for front-end packet management and the SPU is responsible for processing the packet information.
Many prior art processors in the technology area of this patent application use an architecture based on a microprocessor architecture developed by MIPS Technologies. Inc., (referred to herein as a “MIPS compatible processor architecture”), and support commands and instructions compatible with that architecture. However, there are no prior art instruction sets that enable separated functions and coordination between an independently functioning PMU and the processing component described as an SPU.
Also, there are no extended instructions for certain software operations made possible by a unique relationship between components of a DMS system as described in priority document Ser. No. 09/737,375. Therefore a goal of the present invention is to provided an extended set of instructions, which are compatible with a MIPS compatible architecture and also can be used for special capabilities of a DMS processor engaged in the routing of data through a data packet network like the Internet network, for example.